This invention relates to a memory management device. More particularly, it relates to a technique which is effective when utilized in, for example, a memory management unit or a cache controller that is connected to the system bus of a microcomputer system together with a direct memory access controller (DMA controller).
One expedient for removing restrictions attributable to the physical properties of a memory and forming a versatile program system is the virtual store system. In this virtual store system, there is a memory management unit by which a logical or virtual address delivered from a processor is translated into a physical address on the memory.
Such a memory management unit is stated in, for example, "NIKKEI ELECTRONICS" dated Dec. 5, 1983, issued by Nikkei McGraw-Hill Inc., pp. 146-150.
Shown in FIG. 4 is the storing loop of a microcomputer system which employs the virtual store system. Referring to the figure, a microprocessor unit MPU used as a processor is provided with a built-in bus arbiter ABT and has a bus control function The storing loop as viewed from the microprocessor unit MPU is arranged in a continuous virtual address space.
A memory management unit MMU has the function of translating a virtual address VA delivered from the microprocessor unit MPU, into a physical address PA corresponding to the memory area of a main memory MM. The memory area of the main memory MM is divided into pages with a predetermined size. The address translation by the memory management unit MMU is effected on the basis of a so-called paging system wherein, for example, the predetermined upper bits of the virtual address VA are translated into a page address (frame No.) on the physical address PA.
The upper bits of the virtual address VA and the page address on the physical address PA are held in correspondence by a page translation table PTE which is prepared in the main memory MM. The memory management unit MMU realizes the address translation process with reference to this page translation table PTE.
Meanwhile, as the processing ability of the system has been expanded to increase the storage capacity of the main memory MM, there has come into adoption a multi-level paging system wherein the page translation table PTE is stepped into a plurality of levels so as to perform paging processes at the plurality of levels, whereby a memory area to be used for the page translation table is saved. With this system, the number of times which the memory management unit MMU refers to the page translation table PTE enlarges, and the period of time which is required for the address translation process lengthens, so that the processing ability of the system degrades. In order to prevent this drawback, an address translation buffer TLB is employed within the memory management unit MMU.
More specifically, the results of the address translation processes executed by the memory management unit MMU are recorded in the address translation buffer TLB provided within the memory management unit MMU. The memory management unit MMU first refers to the address translation buffer TLB, thereby to try the address translation process. Only in a case where, as a result, a desired address is not recorded in the address translation buffer TLB, that is, the buffer is miss hit, the memory management unit MMU refers to the page translation table PTE within the main memory MM. The address translation buffer TLB is furnished with the required minimum number of entries at which the hit rate thereof reaches a predetermined value. Accordingly, the provision of the address translation buffer TLB raises the speed of the address translation processes of the memory management unit MMU and can suppress the degradation of the processing ability of the system attributed to the adoption of the virtual store system of the multilevel paging system.
The inventors' study, however, has revealed that a problem to be stated below is involved in a case where a direct memory access controller DMAC of low function not having a buffering function, etc., an input/output device having a direct memory access function, or the like is connected in the virtual address space or physical address space in FIG. 4. The input/output device which transfers a series of successive data items between it and the main memory MM or another device through the direct memory access controller DMAC has a data hold time which is permissible according to the operating speed of the input/output device. When the input/output of data has become necessary in the device, the direct memory access controller DMAC sends a bus request signal to the bus arbiter ABT of the microprocessor MPU. On this occasion, when the memory management unit MMU is executing the address translation process based on the page translation table PTE within the main memory MM because of the miss hit of the address translation buffer TLB, the memory access controller DMAC is kept waiting until the address translation process of the memory management unit MMU ends. When a wait time in this case exceeds the data hold time of the device, the various devices fall into error states, and a system bug arises.